Job role : Graduate Intern
Eligibility : M.E/M.Tech
Batch : 2022 / 2023
Location : Bangalore
Last date to apply : ASAP
Eligibility criteria:
Master’s in Hardware Engineering or Electrical/Electronic Engineering or Computer Engineering or Computer Science.
Excellent Problem solving skills combined with good communication skills required to work in a high dynamic cross team and cross site environments.
Ability to learn fast
Qualification:
Usage of any Post-Si debug tools (e.g., logic analyzers, oscilloscopes, things like ChipScope on FPGA’s, etc.).
C/C++ and Python are the most useful languages for our work. o VLSI concepts -Power Management / Reset.
Familiarity with FW (embedded uC) debug ARC or Extensa LX-series uC preferred.
Knowledge of ARM PM concepts (e.g., P/Q-channel).
General clocking concepts (PLL’s, RO’s, etc.).
Ability to debug interactions between different microcontrollers.
Understanding power delivery concepts, VR interactions, etc. -Mesh / Coherency.
Knowledge of coherence algorithm (MESI, MOESI, MESIF, etc.).
Experience with SoC fabrics (AXI, ACE or other AMBA protocols).
Understanding transaction flows through the system. – PCI Express (we can leverage this expertise for other IO’s, like CXL).
Familiarity with any generation of the PCI Express specification o Usage of 3rd party PCIe Analyzers very helpful (Tek, Lecroy, etc.) -Memory.
Expertise in any DDR technology.
Usage of 3rd party DDR Analyzers very helpful (Tek, Lecroy, etc.)
Apply through the link: https://jobs.intel.com/en/job/bengaluru/graduate-intern/41147/49675089696
Comments